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3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC AD7829-1
FEATURES
8-bit half-flash ADC with 420 ns conversion time Eight single-ended analog input channels Available with input offset adjust On-chip track-and-hold SNR performance given for input frequencies up to10 MHz On-chip reference (2.5 V) Automatic power-down at the end of conversion Wide operating supply range 3 V 10% and 5 V 10% Input ranges 0 V to 2 V p-p, VDD = 3 V 10% 0 V to 2.5 V p-p, VDD = 5 V 10% Flexible parallel interface with EOC pulse to allow stand-alone operation
FUNCTIONAL BLOCK DIAGRAM
CONVST EOC A0 A1 A2 VDD
CONTROL LOGIC
COMP
2.5V REF
VMID
AGND
DGND
CS RD
Figure 1.
APPLICATIONS
Data acquisition systems, DSP front ends Disk drives Mobile communication systems, subsampling applications
GENERAL DESCRIPTION
The AD7829-1 is a high speed 8-channel, microprocessorcompatible, 8-bit analog-to-digital converter with a maximum throughput of 2 MSPS. The AD7829-1 contains an on-chip reference of 2.5 V (2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit half-flash ADC; and a high speed parallel interface. The converter can operate from a single 3 V 10% and 5 V 10% supply. The AD7829-1 combines the convert start and power-down functions at one pin, that is, the CONVST pin. This allows a unique automatic power-down at the end of a conversion to be implemented. The logic level on the CONVST pin is sampled after the end of a conversion when an EOC (end of conversion) signal goes high, and if it is logic low at that point, the ADC is powered down. The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. Using only address decoding logic, the parts are easily mapped into the microprocessor address space. The EOC pulse allows the ADCs to be used in a stand-alone manner (see the Parallel Interface section).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The AD7829-1 is available in a 28-lead, wide body, small outline IC (SOIC_W) and a 28-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTS
1. Fast Conversion Time. The AD7829-1 has a conversion time of 420 ns. Faster conversion times maximize the DSP processing time in a real-time system. Analog Input Span Adjustment. The VMID pin allows the user to offset the input span. This feature can reduce the requirements of single-supply op amps and take into account any system offsets. FPBW (Full Power Bandwidth) of Track-and-Hold. The track-and-hold amplifier has excellent high frequency performance. The AD7829-1 is capable of converting fullscale input signals up to a frequency of 10 MHz, making the parts ideally suited to subsampling applications. Channel Selection. Channel selection is made without the necessity of writing to the part.
2.
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4.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
06179-001
VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
BUF
VREF IN/OUT
INPUT MUX
T/H
8-BIT HALF FLASH ADC
PARALLEL PORT
DB7 DB0
AD7829-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Circuit Information ........................................................................ 10 Circuit Description..................................................................... 10 Typical Connection Diagram ................................................... 10 ADC Transfer Function............................................................. 11 Analog Input ............................................................................... 11 Power-Up Times......................................................................... 14 Power vs. Throughput................................................................ 14 Operating Modes........................................................................ 15 Parallel Interface......................................................................... 17 Microprocessor Interfacing........................................................... 18 AD7829-1 to 8051 ...................................................................... 18 AD7829-1 to PIC16C6x/PIC16C7x......................................... 18 AD7829-1 to ADSP-21xx .......................................................... 18 Interfacing Multiplexer Address Inputs .................................. 18 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
7/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD7829-1 SPECIFICATIONS
VDD = 3 V 10%, VDD = 5 V 10%, GND = 0 V, VREF IN/OUT = 2.5 V. All specifications -40C to +85C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio 1 Total Harmonic Distortion1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion1 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation1 DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes Are Guaranteed Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Gain Error1 Gain Error Match1 Offset Error1 Offset Error Match1 ANALOG INPUTS 2 VDD = 5 V 10% VIN1 to VIN8 Input Voltage VMID Input Voltage VDD = 3 V 10% VIN1 to VIN8 Input Voltage VMID Input Voltage VIN Input Leakage Current VIN Input Capacitance VMID Input Impedance REFERENCE INPUT VREF IN/OUT Input Voltage Range Input Current ON-CHIP REFERENCE Reference Error Temperature Coefficient LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Version B 48 -55 -55 -65 -65 -70 8 8 0.75 0.75 2 0.1 1 0.1 Unit dB min dB max dB max fa = 27.3 kHz, fb = 28.3 kHz dB typ dB typ dB typ Bits Bits LSB max LSB max LSB max LSB typ LSB max LSB typ See Analog Input section Input voltage span = 2.5 V VDD 0 VDD - 1.25 1.25 VDD 0 VDD - 1 1 1 15 6 2.55 2.45 1 100 50 50 2.4 0.8 2 0.4 1 10 V max V min V max V min V max V min V max V min A max pF max k typ V max V min A typ A max mV max ppm/C typ V min V max V min V max A max pF max VDD = 5 V 10% VDD = 5 V 10% VDD = 3 V 10% VDD = 3 V 10% Typically 10 nA, VIN = 0 V to VDD Test Conditions/Comments fIN = 30 kHz, fSAMPLE = 2 MHz
fIN = 20 kHz
Default VMID = 1.25 V Input voltage span = 2 V
Default VMID = 1 V
2.5 V + 2% 2.5 V - 2%
Nominal 2.5 V
Rev. 0 | Page 3 of 20
AD7829-1
Parameter LOGIC OUTPUTS Output High Voltage, VOH Version B Unit Test Conditions/Comments ISOURCE = 200 A VDD = 5 V 10% VDD = 3 V 10% ISINK = 200 A VDD = 5 V 10% VDD = 3 V 10%
4 2.4 Output Low Voltage, VOL 0.4 0.2 1 10 200 420 1 4.5 5.5 2.7 3.3 12 5 0.2 36 9.58 23.94
V min V min V max V max A max pF max ns max ns max LSB max V min V max V min V max mA max A max A typ mW max mW typ mW typ
High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Track/Hold Acquisition Time Conversion Time POWER SUPPLY REJECTION VDD 10% POWER REQUIREMENTS VDD VDD IDD Normal Operation Power-Down Power Dissipation Normal Operation Power-Down 200 kSPS 500 kSPS
1 2
See Circuit Description section
5 V 10%; for specified performance 3 V 10%; for specified performance
8 mA typically Logic inputs = 0 V or VDD VDD = 3 V Typically 24 mW
See the Terminology section of this data sheet. Refer to the Analog Input section for an explanation of the analog input(s).
Rev. 0 | Page 4 of 20
AD7829-1
TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications -40C to +85C, unless otherwise noted. Table 2.
Parameter1, 2 t1 t2 t3 t4 t5 t6 t7 t8 t93 t104 t11 t12 t13 tPOWER UP tPOWER UP
1 2
5 V 10% 420 20 30 110 70 10 0 0 30 10 5 20 10 15 200 25 1
3 V 10% 420 20 30 110 70 10 0 0 30 20 5 20 10 15 200 25 1
Unit ns max ns min ns min ns max ns min ns max ns min ns min ns min ns max ns min ns max ns min ns min ns min s typ s max
Description Conversion time Minimum CONVST pulse width Minimum time between the rising edge of RD and the next falling edge of convert start EOC pulse width RD rising edge to EOC pulse high CS to RD setup time CS to RD hold time Minimum RD pulse width Data access time after RD low Bus relinquish time after RD high Address setup time before the falling edge of RD Address hold time after the falling edge of RD Minimum time between new channel selection and convert start Power-up time from the rising edge of CONVST using on-chip reference Power-up time from the rising edge of CONVST using external 2.5 V reference
Sample tested to ensure compliance. See Figure 21, Figure 22, and Figure 23. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V 10%, and the time required for an output to cross 0.4 V or 2.0 V with VDD = 3 V 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200A IOL
TO OUTPUT PIN
2.1V CL 50pF 200A IOH
06179-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. 0 | Page 5 of 20
AD7829-1 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND VIN1 to VIN8 Reference Input Voltage to AGND VMID Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature SOIC Package, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) TSSOP Package, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 450 mW 75C/W 215C 220C 450 mW 128C/W 215C 220C 1 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD7829-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DB2 1 DB1 2 DB0 3 CONVST 4 CS 5 RD 6
28 27 26 25 24
DB3 DB4 DB5 DB6 DB7
DGND 7 A2 9
AGND TOP VIEW 22 V DD (Not to Scale) 21 VREF IN/OUT EOC 8
23 20 19 18 17 16 15
AD7829-1
VMID VIN1 VIN2 VIN3 VIN5
06179-003
A1 10 A0 11 VIN8 12 VIN7 13 VIN6 14
VIN4
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 12 to 19 Mnemonic VIN8 to VIN1 Description Analog Input Channels. The AD7829-1 has eight analog input channels. The inputs have an input span of 2.5 V and 2 V, depending on the supply voltage (VDD). This span can be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V 10%) or AGND to 2.5 V (VDD = 5 V 10%). See the Analog Input section of the data sheet for more information. Positive Supply Voltage, 3 V 10% and 5 V 10%. Analog Ground. Ground reference for track/hold, comparators, reference circuit, and multiplexer. Digital Ground. Ground reference for digital circuitry. Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7829-1 powers down (see the Operating Modes section). Logic Output. The end of conversion signal indicates when a conversion has finished. The signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section). Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7829. This is necessary if the ADC is sharing a common data bus with another device. Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus. Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal goes low. Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and CS go active low. Analog Input and Output. An external reference can be connected to the AD7829-1 at this pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 F capacitor. The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog Input section).
22 23 7 4
VDD AGND DGND CONVST
8
EOC
5 6
CS RD
9 to 11 1 to 3, 24 to 28 21
A2 to A0 DB2 to DB0, DB7 to DB3 VREF IN/OUT
20
VMID
Rev. 0 | Page 7 of 20
AD7829-1 TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for an 8-bit converter, this is 50 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7829-1 it is defined as
THD (dB) = 20 log V2 + V3 + V4 + V5 + V6
2 2 2 2 2
As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels (dB). Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is measured by applying a full-scale 20 kHz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The figure given is the worst case across all eight channels of the AD7829-1. Relative Accuracy or Endpoint Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the 128th code transition (01111111) to (10000000) from the ideal, that is, VMID. Offset Error Match The difference in offset error between any two channels. Zero-Scale Error The deviation of the first code transition (00000000) to (00000001) from the ideal; that is, VMID - 1.25 V + 1 LSB (VDD = 5 V 10%), or VMID - 1.0 V + 1 LSB (VDD = 3 V 10%). Full-Scale Error The deviation of the last code transition (11111110) to (11111111) from the ideal; that is, VMID + 1.25 V - 1 LSB (VDD = 5 V 10%), or VMID + 1.0 V - 1 LSB (VDD = 3 V 10%). Gain Error The deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal; that is, VREF - 1 LSB, after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels.
V1
where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3... . Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7829-1 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies.
Rev. 0 | Page 8 of 20
AD7829-1
Track/Hold Acquisition Time The time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the point at which the track/hold returns to track mode. This happens approximately 120 ns after the falling edge of CONVST. It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VIN input of the AD7829-1. It means that the user must wait for the duration of the track/hold acquisition time after a channel change/step input change to VIN before starting another conversion, to ensure that the part operates to specification. PSR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the converter's linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value.
Rev. 0 | Page 9 of 20
AD7829-1 CIRCUIT INFORMATION
CIRCUIT DESCRIPTION
The AD7829-1 consists of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. These devices use a half-flash conversion technique where one 4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash ADC contains a sampling capacitor followed by 15 comparators that compare the unknown input to a reference ladder to achieve a 4-bit result. This first flash, that is, coarse conversion, provides the four MSBs. For a full 8-bit reading to be realized, a second flash, that is, a fine conversion, must be performed to provide the four LSBs. The 8-bit word is then placed on the data output bus. Figure 4 and Figure 5 show simplified schematics of the ADC. When the ADC starts a conversion, the track-and-hold goes into hold mode and holds the analog input for 120 ns. This is the acquisition phase as shown in Figure 4, when Switch 2 is in Position A. At the point when the track-and-hold returns to its track mode, this signal is sampled by the sampling capacitor as Switch 2 moves into Position B. The first flash occurs at this instant and is then followed by the second flash. Typically, the first flash is complete after 100 ns, that is, at 220 ns, while the end of the second flash and, hence, the 8-bit conversion result, is available at 330 ns (minimum). The maximum conversion time is 420 ns. As shown in Figure 6, the track-and-hold returns to track mode after 120 ns and starts the next acquisition before the end of the current conversion. Figure 8 shows the ADC transfer function.
REFERENCE
REFERENCE
R16 15 R15 D7 D6 14 B HOLD SAMPLING CAPACITOR R14 R13 D1 1 R1 TIMING AND CONTROL LOGIC D0 13 D5
OUTPUT REGISTER
OUTPUT DRIVERS
DECODE LOGIC
VIN
T/H 1
A
SW2
D4 D3 D2
Figure 5. ADC Conversion Phase
120ns
TRACK HOLD TRACK HOLD
CONVST EOC CS
t2 t1
RD
VALID DATA
t3
06179-007
DB0 TO DB7
Figure 6. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
R16 15 R15 D7 D6 14 B HOLD SAMPLING CAPACITOR R14 R13 D1 1 R1 TIMING AND CONTROL LOGIC D0 13 D5
OUTPUT REGISTER
OUTPUT DRIVERS
DECODE LOGIC
VIN
T/H 1
A
SW2
D4 D3 D2
Figure 4. ADC Acquisition Phase
Figure 7 shows a typical connection diagram for the AD7829-1. The AGND and DGND are connected together at the device for good noise suppression. The parallel interface is implemented using an 8-bit data bus. The end of conversion signal (EOC) idles high, the falling edge of CONVST initiates a conversion, and at the end of conversion the falling edge of EOC is used to initiate an interrupt service routine (ISR) on a microprocessor (see the Parallel Interface section). VREF IN/OUT and VMID are connected to a voltage source, such as the AD780, while VDD is connected to a voltage source that can vary from 4.5 V to 5.5 V (see Table 5 in the Analog Input section). When VDD is first connected, the AD7829-1 powers up in a low current mode, that is, power-down. Ensure that the CONVST line is not floating when VDD is applied, because this can put the AD7829-1 into an unknown state.
Rev. 0 | Page 10 of 20
06179-005
06179-006
AD7829-1
A suggestion is to tie CONVST to VDD or DGND through a pull-up or pull-down resistor. A rising edge on the CONVST pin causes the AD7829-1 to fully power up. For applications where power consumption is of concern, the automatic powerdown at the end of a conversion should be used to improve power performance (see the Power vs. Throughput section). If the AD7829-1 is operated outside normal VDD limits (for example, a brown-out), it may take two conversions to reset the part once the correct VDD has been established.
SUPPLY 4.5V TO 5.5V 2.5V AD780 10F 0.1F PARALLEL INTERFACE VREF VMID
ANALOG INPUT
The AD7829-1 has eight input channels. Each input channel has an input span of 2.5 V or 2.0 V, depending on the supply voltage (VDD). This input span is automatically set up by an on-chip "VDD detector" circuit. A 5 V operation of the ADCs is detected when VDD exceeds 4.1 V, and a 3 V operation is detected when VDD falls below 3.8 V. This circuit also possesses a degree of glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to 60 ns wide does not trip the VDD detector. The VMID pin is used to center this input span anywhere in the range of AGND to VDD. If no input voltage is applied to VMID, the default input range is AGND to 2.0 V (VDD = 3 V 10%), that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V 10%), that is, centered about 1.25 V. When using the default input range, the VMID pin can be left unconnected; or, in some cases, it can be decoupled to AGND with a 0.1 F capacitor. If, however, an external VMID is applied, the analog input range is from VMID - 1.0 V to VMID + 1.0 V (VDD = 3 V 10%), or from VMID - 1.25 V to VMID + 1.25 V (VDD = 5 V 10%). The range of values of VMID that can be applied depends on the value of VDD. For VDD = 3 V 10%, the range of values that can be applied to VMID is from 1.0 V to VDD - 1.0 V and is 1.25 V to VDD - 1.25 V when VDD = 5 V 10%. Table 5 shows the relevant ranges of VMID and the input span for various values of VDD. Figure 9 illustrates the input signal range available with various values of VMID. Table 5.
VDD 5.5 5.0 4.5 3.3 3.0 2.7 VMID Internal 1.25 1.25 1.25 1.00 1.00 1.00 VMID Ext Maximum 4.25 3.75 3.25 2.3 2.0 1.7 VIN Span 3.0 to 5.5 2.5 to 5.0 2.0 to 4.5 1.3 to 3.3 1.0 to 3.0 0.7 to 2.7 VMID Ext Minimum 1.25 1.25 1.25 1.00 1.00 1.00 VIN Span 0 to 2.5 0 to 2.5 0 to 2.5 0 to 2.0 0 to 2.0 0 to 2.0
VDD
DB0 TO DB7 1.25V TO 3.75V INPUT VIN1 VIN2 EOC
AD7829-1
RD CS C/P CONVST A0
VIN8 AGND
A1 A2
06179-008
DGND
Figure 7. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7829-1 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to VREF/256 (VDD = 5 V), or the LSB size is equal to (0.8 VREF)/256 (VDD = 3 V). The ideal transfer characteristic for the AD7829-1 is shown in Figure 8.
11111111 111...110 ADC CODE 111...000 10000000 000...111 000...010 000...001 00000000 (VDD = 3V) 1LSB = 0.8VREF /256 (VDD = 5V) 1LSB = VREF /256
1LSB
VMID
06179-009
(VDD = 5V) VMID - 1.25V (VDD = 3V) VMID - 1V
VMID + 1.25V - 1LSB VMID + 1V - 1LSB
ANALOG INPUT VOLTAGE
Figure 8. Transfer Characteristic
Rev. 0 | Page 11 of 20
AD7829-1
2.5V
VDD = 5V 5V
R4 VREF VMID
4V VMID = 3.75V 3V VMID = 2.5V 2V VMID = N/C (1.25V) 1V INPUT SIGNAL RANGE FOR VARIOUS VMID
V V
AD7829-1
VIN
R3 R2 R1 VIN 2.5V
06179-012
0V
0V
Figure 11. Accommodating Bipolar Signals Using External VMID
EXTERNAL 2.5V
VDD = 3V 3V
VREF VMID R4
2V VMID = 2V VMID = 1.5V 1V VMID = N/C (1V) INPUT SIGNAL RANGE FOR VARIOUS VMID
V V
R3 R2 R1 VIN
06179-010
AD7829-1
VIN
0V
VMID
06179-013
Figure 9. Analog Input Span Variation with VMID
0V
VMID can be used to remove offsets in a system by applying the offset to the VMID pin, as shown in Figure 10; or it can be used to accommodate bipolar signals by applying VMID to a level-shifting circuit before VIN, as shown in Figure 11. When VMID is being driven by an external source, the source can be directly tied to the level-shifting circuitry (see Figure 11); however, if the internal VMID, that is, the default value, is being used as an output, it must be buffered before applying it to the level-shifting circuitry, because the VMID pin has an impedance of approximately 6 k (see Figure 12).
VIN VIN
Figure 12. Accommodating Bipolar Signals Using Internal VMID
NOTE: Although there is a VREF pin from which a voltage reference of 2.5 V can be sourced, or to which an external reference can be applied, this does not provide an option of varying the value of the voltage reference. As stated in the specifications for the AD7829-1, the input voltage range at this pin is 2.5 V 2%.
Analog Input Structure
Figure 13 shows an equivalent circuit of the analog input structure of the AD7829-1. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This causes these diodes to become forward biased and start conducting current into the substrate. 20 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. However, it is worth noting that a small amount of current (1 mA) conducted into the substrate due to an overvoltage on an unselected channel can cause inaccurate conversions on a selected channel.
VMID
AD7829-1
VMID
06179-011
VMID
Figure 10. Removing Offsets Using VMID
Rev. 0 | Page 12 of 20
AD7829-1
Capacitor C2 in Figure 13 is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor, R1, is a lumped component made up of the on resistance of several components, including that of the multiplexer and the trackand-hold. This resistor is typically about 310 . Capacitor C1 is the track-and-hold capacitor and has a capacitance of 0.5 pF. Switch 1 is the track-and-hold switch, while Switch 2 is that of the sampling capacitor, as shown in Figure 4 and Figure 5.
VDD C1 0.5pF A SW2 SW1 B
06179-014
120ns TRACK CHx HOLD CHx TRACK CHx TRACK CHy HOLD CHy
t2
CONVST
t1
EOC
CS
RD
t3 t13
D1 VIN
R1 310
DB0 TO DB7
VALID DATA
C2 4pF
D2
ADDRESS CHANNEL y
Figure 14. Channel Hopping Timing
Figure 13. Equivalent Analog Input Circuit
When in track phase, Switch 1 is closed and Switch 2 is in Position A; when in hold mode, Switch 1 opens, while Switch 2 remains in Position A. The track-and-hold remains in hold mode for 120 ns (see the Circuit Description section), after which it returns to track mode and the ADC enters its conversion phase. At this point, Switch 1 opens and Switch 2 moves to Position B. At the end of the conversion, Switch 2 moves back to Position A.
There is a minimum time delay between the falling edge of RD and the next falling edge of the CONVST signal, t13. This is the minimum acquisition time required of the track-and-hold to maintain 8-bit performance. Figure 15 shows the typical performance of the AD7829-1 when channel hopping for various acquisition times. These results were obtained using an external reference and internal VMID while channel hopping between VIN1 and VIN4 with 0 V on Channel 4 and 0.5 V on Channel 1.
8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 500
Analog Input Selection
On power-up, the default VIN selection is VIN1. When returning to normal operation from power-down, the VIN selected is the same one that was selected prior to power-down being initiated. Table 6 shows the multiplexer address corresponding to each analog input from VIN1 to VIN8 for the AD7829-1. Table 6.
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Analog Input Selected VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
ENOB
200
100
50 40 30 20 ACQUISITION TIME (ns)
15
10
Figure 15. Effective Number of Bits vs. Acquisition Time for the AD7829-1
Channel selection on the AD7829-1 is made without the necessity of a write operation. The address of the next channel to be converted is latched at the start of the current read operation, that is, on the falling edge of RD while CS is low, as shown in Figure 14. This allows for improved throughput rates in "channel hopping" applications.
The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7829-1 ideal for subsampling applications. When the AD7829-1 is converting a 10 MHz input signal at a sampling rate of 2 MSPS, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dB, as shown in Figure 16.
Rev. 0 | Page 13 of 20
06179-016
06179-015
A0 TO A2
AD7829-1
50
fSAMPLE = 2MHz
48
46
44
42
40 38 0.2
If the falling edge of CONVST occurs after the required powerup time has elapsed, then it is upon this falling edge that a conversion is initiated. When using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 s before initiating a conversion. That is, a falling edge on CONVST must not occur before the required power-up time has elapsed, when VDD is first connected or after the AD7829-1 has been powered down using the CONVST pin, as shown in Figure 17.
SNR (dB)
POWER VS. THROUGHPUT
06179-017
1
3 4 5 6 INPUT FREQUENCY (MHz)
8
10
Figure 16. SNR vs. Input Frequency on the AD7829-1
Superior power performance can be achieved by using the automatic power-down (Mode 2) at the end of a conversion (see the Operating Modes section). Figure 18 shows how the automatic power-down is implemented using the CONVST signal to achieve the optimum power performance for the AD7829-1. The duration of the CONVST pulse is set to be equal to or less than the power-up time of the devices (see the Operating Modes section). As the throughput rate is reduced, the device remains in its power-down state longer, and the average power consumption over time drops accordingly.
tPOWER-UP tCONVERT
1s CONVST 330ns POWER-DOWN
POWER-UP TIMES
The AD7829-1 has a 1 s power-up time when using an external reference and a 25 s power-up time when using the on-chip reference. When VDD is first connected, the AD7829-1 is in a low current mode of operation. Ensure that the CONVST line is not floating when VDD is applied. If there is a glitch on CONVST while VDD is rising, the part attempts to power up before VDD has fully settled and may enter an unknown state. In order to carry out a conversion, the AD7829-1 must first be powered up.
EXTERNAL REFERENCE
VDD
tCYCLE
10s @ 100kSPS
tPOWER-UP
1s
Figure 18. Automatic Power-Down
CONVST CONVERSION INITIATED HERE
ON-CHIP REFERENCE
VDD
tPOWER-UP
25s
CONVST CONVERSION INITIATED HERE
06179-018
Figure 17. AD7829-1 Power-Up Time
The AD7829-1 is powered up by a rising edge on the CONVST pin. A conversion is initiated on the falling edge of CONVST. Figure 17 shows how to power up the AD7829-1 when VDD is first connected or after the AD7829-1 has been powered down using the CONVST pin when using either the on-chip reference or an external reference. When using an external reference, the falling edge of CONVST may occur before the required powerup time has elapsed. However, the conversion is not initiated on the falling edge of CONVST but rather at the moment when the part has completely powered up, that is, after 1 s.
For example, if the AD7829-1 is operated in a continuous sampling mode, with a throughput rate of 100 kSPS and using an external reference, the power consumption is calculated as follows. The power dissipation during normal operation is 36 mW, VDD = 3 V. If the power-up time is 1 s and the conversion time is 330 ns (@ +25C), the AD7829-1 can be said to dissipate 36 mW (maximum) for 1.33 s during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 s and the average power dissipated during each cycle is (1.33/10) x (36 mW) = 4.79 mW. This calculation uses the minimum conversion time, thus giving the best-case power dissipation at this throughput rate. However, the actual power dissipated during each conversion cycle may increase, depending on the actual conversion time (up to a maximum of 420 ns).
Rev. 0 | Page 14 of 20
06179-019
AD7829-1
Figure 19 shows the power vs. throughput rate for automatic, full power-down.
100
OPERATING MODES
The AD7829-1 has two possible modes of operation, depending on the state of the CONVST pulse approximately 100 ns after the end of a conversion, that is, upon the rising edge of the EOC pulse.
10 POWER (mW)
Mode 1 Operation (High-Speed Sampling)
When the AD7829-1 is operated in Mode 1, it is not powered down between conversions. This mode of operation allows high throughput rates to be achieved. Figure 21 shows how this optimum throughput rate is achieved by bringing CONVST high before the end of a conversion, that is, before the EOC pulses low. When operating in this mode, a new conversion should not be initiated until 30 ns after the end of a read operation. This allows the track/hold to acquire the analog signal to 0.5 LSB accuracy.
1
0.1
0
50
100
150 200 250 300 350 THROUGHPUT (kSPS)
400
450
500
Figure 19. AD7829-1 Power vs. Throughput
0 -10 -20 -30 2048 POINT FFT SAMPLING 2MSPS fIN = 200kHz
06179-020
0
Mode 2 Operation (Automatic Power-Down)
When the AD7829-1 is operated in Mode 2 (see Figure 22), it automatically powers down at the end of a conversion. The CONVST signal is brought low to initiate a conversion and is left logic low until after the EOC goes high, that is, approximately 100 ns after the end of the conversion. The state of the CONVST signal is sampled at this point (that is, 530 ns maximum after CONVST falling edge) and the AD7829-1 powers down as long as CONVST is low. The ADC is powered up again on the rising edge of the CONVST signal. Superior power performance can be achieved in this mode of operation by powering up the AD7829-1 only to carry out a conversion. The parallel interface of the AD7829-1 is still fully operational while the ADCs are powered down. A read can occur while the part is powered down, and so it does not necessarily need to be placed within the EOC pulse, as shown in Figure 22.
TRACK HOLD
(dB)
-40 -50 -60 -70 -80
0 28 57 85 113 142 170 198 227 255 283 312 340 368 396 425 453 481 510 538 566 595 623 651 680 708 736 765 793 821 850 878 906 935 963 991
FREQUENCY (kHz)
Figure 20. AD7829-1 SNR
120ns TRACK HOLD
t2
CONVST
t1
EOC
CS
06179-021
t3
RD
DB0 TO DB7
VALID DATA
Figure 21. Mode 1 Operation
Rev. 0 | Page 15 of 20
06179-022
AD7829-1
tPOWER-UP
CONVST POWER DOWN HERE
t1
EOC
CS
RD
DB0 TO DB7
VALID DATA
Figure 22. Mode 2 Operation
Rev. 0 | Page 16 of 20
06179-023
AD7829-1
PARALLEL INTERFACE
The parallel interface of the AD7829-1 is eight bits wide. Figure 23 shows a timing diagram illustrating the operational sequence of the AD7829-1 parallel interface. The multiplexer address is latched into the AD7829-1 on the falling edge of the RD input. The onchip track/hold goes into hold mode on the falling edge of CONVST. A conversion is also initiated at this point. When the conversion is complete, the end of conversion line (EOC) pulses low to indicate that new data is available in the output register of the AD7829-1. The EOC pulse stays logic low for a maximum time of 110 ns.
t2
CONVST
However, the EOC pulse can be reset high by a rising edge of RD. This EOC line can be used to drive an edge-triggered interrupt of a microprocessor. CS and RD going low accesses the 8-bit conversion result. It is possible to tie CS permanently low and use only RD to access the data. In systems where the part is interfaced to a gate array or ASIC, this EOC pulse can be applied to the CS and RD inputs to latch data out of the AD7829-1 and into the gate array or ASIC. This means that the gate array or ASIC does not need any conversion status recognition logic, and it also eliminates the logic required in the gate array or ASIC to generate the read signal for the AD7829-1.
t1
EOC
t4
t5
CS
t6
RD
t7 t8 t9 t10
VALID DATA
t3
DB0 TO DB7
t11
A0 TO A2
t12
t13
Figure 23. AD7829-1 Parallel Port Timing
Rev. 0 | Page 17 of 20
06179-024
NEXT CHANNEL ADDRESS
AD7829-1 MICROPROCESSOR INTERFACING
The parallel port on the AD7829-1 allows the ADCs to be interfaced to a range of many different microcontrollers. This section explains how to interface the AD7829-1 with some of the more common microcontroller parallel interface protocols.
PIC16C6x/7x1
AD7829-11
PSP0 TO PSP7
DB0 TO DB7
AD7829-1 TO 8051
Figure 24 shows a parallel interface between the AD7829-1 and the 8051 microcontroller. The EOC signal on the AD7829-1 provides an interrupt request to the 8051 when a conversion ends and data is ready. Port 0 of the 8051 can serve as an input or output port, or, as in this case when used together with the address latch enable (ALE) of the AD8051, it can be used as a bidirectional low order address and data bus. The ALE output of the 8051 is used to latch the low byte of the address during accesses to the device, while the high order address byte is supplied from Port 2. Port 2 latches remain stable when the AD7829-1 is addressed, because they do not have to be turned around (set to 1) for data input, as is the case for Port 0.
80511
CS
CS
RD INT
1ADDITIONAL
RD EOC
06179-026
PINS OMITTED FOR CLARITY.
Figure 25. Interfacing to the PIC16C6x/PIC16C7x
AD7829-1 TO ADSP-21xx
Figure 26 shows a parallel interface between the AD7829-1 and the ADSP-21xx series of DSPs. As before, the EOC signal on the AD7829-1 provides an interrupt request to the DSP when a conversion ends.
ADSP-21xx1
D7 TO D0 DB0 TO DB7
DB0 TO DB7
AD0 TO AD7 LATCH DECODER
AD7829-11
CS
A13 TO A0 ADDRESS DECODE LOGIC DMS EN CS RD EOC
06179-027
AD7829-11
ALE A8 TO A15 RD INT
1ADDITIONAL
RD
06179-025
RD IRQ
1ADDITIONAL
EOC
PINS OMITTED FOR CLARITY.
PINS OMITTED FOR CLARITY.
Figure 24. Interfacing to the 8051
Figure 26. Interfacing to the ADSP-21xx
AD7829-1 TO PIC16C6x/PIC16C7x
Figure 25 shows a parallel interface between the AD7829-1 and the PIC16C64/PIC16C65/PIC16C74. The EOC signal on the AD7829-1 provides an interrupt request to the microcontroller when a conversion begins. Of the PIC16C6x/PIC16C7x range of microcontrollers, only the PIC16C64/PIC16C65/PIC16C74 can provide the option of a parallel slave port. Port D of the microcontroller operates as an 8-bit wide parallel slave port when Control Bit PSPMODE in the TRISE register is set. Setting PSPMODE enables Port Pin RE0 to be the RD output and RE2 to be the CS (chip select) output. For this functionality, the corresponding data direction bits of the TRISE register must be configured as outputs (reset to 0). See the PIC16C6x/PIC16C7x Microcontroller User Manual for more information.
INTERFACING MULTIPLEXER ADDRESS INPUTS
Figure 27 shows a simplified interfacing scheme between the AD7829-1 and any microprocessor or microcontroller that facilitates easy channel selection on the ADCs. The multiplexer address is latched on the falling edge of the RD signal, as outlined in the Parallel Interface section, which allows the use of the three LSBs of the address bus to select the channel address. As shown in Figure 27, only Address Bit A3 to Address Bit A15 are address decoded, allowing A0 to A2 to be changed according to desired channel selection without affecting chip selection.
Rev. 0 | Page 18 of 20
AD7829-1
AD7829-11
A0 A1 A2 A15 TO A3 ADDRESS DECODE CS A15 TO A3 RD A2 TO A0 DB7 TO DB0 DB0 TO DB7 A/D RESULT
06179-028
MICROPROCESSOR READ CYCLE
CS RD ADC I/O ADDRESS
SYSTEM BUS
MUX ADDRESS
MUX ADDRESS (CHANNEL SELECTION A0 TO A2) LATCHED
Figure 27. AD7829-1 Simplified Microinterfacing Scheme
Rev. 0 | Page 19 of 20
AD7829-1 OUTLINE DIMENSIONS
18.10 (0.7126) 17.70 (0.6969)
28 15
7.60 (0.2992) 7.40 (0.2913)
1 14
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0
45
SEATING PLANE
0.33 (0.0130) 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches)
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 29. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7829BRU-1 AD7829BRU-1REEL7 AD7829BRUZ-1 1 AD7829BRUZ-1REEL71 AD7829BRW-1 AD7829BRW-1RL7 AD7829BRWZ-11 AD7829BRWZ-1RL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W]
Package Option RU-28 RU-28 RU-28 RU-28 RW-28 RW-28 RW-28 RW-28
060706-A
Linearity Error 0.75 LSB 0.75 LSB 0.75 LSB 0.75 LSB 0.75 LSB 0.75 LSB 0.75 LSB 0.75 LSB
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06179-0-7/06(0)
Rev. 0 | Page 20 of 20

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